| Type |
Instruction Fetch |
Instruction Decode |
Execution |
Memory Access |
Completion |
Cycles |
| R-type |
IR = Memory[PC]
PC = PC + 1 |
A = Reg[ IR[11-9] ]
B = Reg[ IR[8-6] ]
ALUOut = PC + SE(IR[5-0]) |
ALUOut = A op B |
Reg[IR[5-3]] = ALUOut |
|
4 |
| andi ori |
ALUOut = A op ZE(IR[7-0]) |
Reg[IR[11-9]] = ALUOut |
|
4 |
| lui |
Reg[IR[11-9]] = IR[7-0] || 00000000 |
|
|
3 |
| sll |
Reg[IR[8-6]] = A << IR[5-0] |
|
|
3 |
| srl |
Reg[IR[8-6]] = A >> IR[5-0] |
|
|
3 |
| lw |
ALUOut = A + SE(IR[5-0]) |
MDR = Memory[ALUOut] |
Reg[IR[8-6]] = MDR |
5 |
| sw |
Memory[ALUOut] = B |
|
4 |
| lwra |
RA = Memory[ALUOut] |
|
4 |
| swra |
Memory[ALUOut] = RA |
|
4 |
| beq bne |
ALUOut = A - B
MDR = ALUOut |
if(ALU.Z)
then PC = MDR |
|
4 |
| j |
PC = PC[15-12] || IR[11-0] |
|
|
3 |
| jal |
RA = PC
PC = PC[15-12] || IR[11-0] |
|
|
3 |
| jr |
PC = A |
|
|
3 |
| jra |
PC = RA |
|
|
3 |
| jm |
ALUOut = A + SE(IR[7-0]) |
PC = Memory[ALUOut] |
|
4 |
| MTM |
ALUOut = A + SE(IR[5-0]) |
MDR = Memory[ALUOut] |
Memory[B] = MDR |
5 |
| MTMz |
MDR = Memory[A] |
Memory[B] = MDR |
|
4 |
| swap |
Reg[IR[8-6]] = A |
Reg[IR[11-9]] = B |
|
4 |
| copy |
|
|
3 |