Control Signals

The control signals listed below are output by the control module depending on the current instruction and cycle.

Name Selects Values
IorD input address to Memory module
0   PC
1   ALUOut
2   B
3   A
MemSrc data to write to memory
0   B
1   RA
2   MDR
MemWrite enables writing to memory
0   do not write to memory
1   write to memory
PCWrite enables writing to the PC register
0   do not write to PC
1   write to PC
IsBranch whether this instruction and cycle is a branch
(whether to update PC)
0   this instruction is beq or bne
1   not a branch statement
PCWriteCond type of branch
0   for beq: branch if ALU outputs zero
1   for bne: branch if ALU does not output zero
PCSource source for new PC value
0   ALUOut
1   ALU output
2   A
3   PC[ 15 - 12 ] || IR[ 11 - 0 ]
4   Memory.MemData (data read from memory)
5   MDR
6   RA
RASource source of new RA value
0   Memory.Memdata (data read from memory)
1   PC
RAWrite whether to write to the RA register
0   do not write to RA
1   write to RA
MDRSrc data to write to MDR
0   Memory.Memdata (data read from memory)
1   ALU output
IRWrite whether to write to IR register
0   do not write to IR
1   write to IR
ImmSrc source for immediate value (which bits of IR)
0   IR[ 7 - 0 ]
1   IR[ 5 - 0 ]
RegDst destination register address
0   IR[ 11 - 9 ]
1   IR[ 8 - 6 ]
2   IR[ 5 - 3 ]
MemToReg register file write data
0   A >> IR[ 5 - 0 ]
1   A << IR[ 5 - 0 ]
2   IR[ 8 - 0 ] || 0x00
3   MDR
4   ALUOut
5   A
6   B
ALUSrcA source data A to ALU
0   PC
1   A
2   B
ALUSrcB source data B to ALU
0   B
1   0x0001
2   SE( immediate )