In order to break up the datapath design into stages and to ensure that removing non-core instructions will not require redesigning the datapath, we chose to design the datapath separately for each instruction type and each cycle, and add the control (such as multiplexors) afterwards.
| Type | Instruction Fetch | Instruction Decode | Execution | Memory Access | Completion | Cycles |
|---|---|---|---|---|---|---|
| R-type | 4 | |||||
| I-type | 4 | |||||
| lui | 3 | |||||
| sll | 3 | |||||
| srl | 3 | |||||
| lw | 5 | |||||
| sw | 4 | |||||
| lwra | 4 | |||||
| swra | 4 | |||||
| Branch | 3 | |||||
| j | 3 | |||||
| jal | 3 | |||||
| jr | 3 | |||||
| jm | 4 | |||||
| mtm | 5 | |||||
| mtmz | 4 | |||||
| swap | 4 | |||||
| copy | 3 |