We successfully designed an instruction set, implemented the datapath and control for it, and designed an assembler during the last 5 weeks of the academic quarter. We have tested all of our instructions and ran the benchmarks proposed by our professors. We based our design on MIPS, and made changes that we felt would improve either performance or flexibility.
Our first decision not to conform to MIPS was to use word (where 16 bits is a word) addressing rather than byte addressing. We chose this because it is very rare to need to refer to the middle of a word at the instruction level, and this requires fewer bits to access the same address.
Since we were limited to a 16-bit data bus, we decided to use 16-bit instructions for simplicity of design. This made it very difficult to fit everything we wanted into the instructions. We eventually decided to use 4 bits for the op-code and 3 bits for register addresses. Any remaining bits would be specific to instruction type.
We also wanted to include a direct memory-to-memory copy, becuase we realized that writing to the register file and reading back was wasteful, and copying memory is common. We were able to achieve a copy in the same number of cycles as reading from memory.
To save register numbers (3 bits only allow for 8), we decided not to give a number to the return address register RA. We chose this register because it is normally updated by jump-and-link and always from either the program counter or memory. To accomodate for this, we added two instructions: load-word-RA (lwra) and store-word-RA (swra).
Given more time we could have implemented shortcuts to save cycles when immediate values are identically zero, designed pseudoinstructions that the assembler could substitute real instructions for, or even design an emulator. We also could perform more testing and slight variations to our design to optimize performance.