Implementation

We implemented our processor in the Xilinx Foundation Series software package. All of the non-trivial modules we created are shown in the table below.

File Description
processor.pdf Schematic of entire processor. This contains modules provided by Xilinx and modules created by us.
controlstatemachine.pdf Finite state machine for the control module.
ALU.v Verilog module that implements an ALU with carry look-ahead.
RegisterFile.v Verilog module that implements a 16-register file of 16-bit registers that supports reading two registers or writing one register at the same time.
InstructionRegister.v Verilog module that interfaces to a single 16-bit register giving us the bus pins that we desire.
Shifter.v Verilog module that performs logical right and left shifts.

 

Xilinx Project Files

The zip files below are archived Xilinx projects from various stages of development. There is at least one archive for each design level.

File Date Description
zip January 24, 2002 Initial implementation of datapath. Control not implemented.
zip February 7, 2002 Initial implementation of datapath and control for simple R-type instructions. Untested.
zip February 10, 2002 Levels 1 and 2 fully implemented. ori and add seem to work. No formal testing, but some test cases look good.
zip February 11, 2002 Level 3 implemented. Verified lui, sub, and, or.
zip February 12, 2002 Level 4 implemented. Verified beq, bne.
zip February 12, 2002 Level 5 implemented. Verified j, jal, jr.
zip February 12, 2002 Level 6 implemented. Verified lw, sw, lwra, swra.
zip February 12, 2002 Everything through Level 8 implemented. Verified all instructions. mult and div have not been implemented.

 

Implementation Speed

Minimum period   101.497 ns
Maximum net delay   29.230 ns
Clock speed   9.853 MHz

 

We could not implement this design on the 4010XLPC84 device becuase we required at least 719 CLBs (Combinational Logic Blocks) and only 400 are available. We chose instead to implement our design on the 4028XLHQ240-09.

Device Usage

Resource Used Available Percent Used
CLBs 827 1024 80.8%
CLB flip flops 229 2048 11.2%
4-input LUTs 1426 2048 69.6%
3-input LUTs 488 1024 47.7%
TBUFs 128 2176 5.88%
External IOBs 34 193 17.6%